This page provides detailed information about the Imperas Instruction Set Simulator for the MIPS 1004Kf processor core.
Processor IP owner is MIPS. More information is available from them here.
The Imperas Instruction Set Simulator (ISS) is a product of Imperas Software Ltd. It is a binary licensed by Imperas as a commercial product. It is also available in OVP packages for evaluation and demonstration.
The Imperas ISS uses the OVP Fast Processor Models and dynamically loads them as selected.The OVP Fast Processor Models are written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The processor models are provided as a binary shared object and are also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The models have been run through an extensive QA and regression testing process.
If you develop your own processor models using the OVP VMI APIs then they can be used with the Imperas ISS.
Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here. Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.
This ISS executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The ISS also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
The ISS is downloadable (needs registration and to be logged in) in package Demo_Processors for Windows32 and for Linux32. Note that the ISS is also available for 64 bit hosts as part of the commercial products from Imperas.
This ISS uses the CPU with Model Variant name: 1004Kf
MIPS32 Configurable Processor Model
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
Cache model does not implement coherency
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
only MIPS32 Instruction set implemented
MMU Type: Standard TLB
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Vectored interrupts implemented
MIPS16e ASE implemented
MT ASE implemented
DSP ASE implemented
The CPU model being used is downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32. Note that the CPU model is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the OVP simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant (1004Kf) being used in this ISS is available OVP_Model_Specific_Information_mips32_r1r5_1004Kf.pdf.
For more information on the Imperas ISS see the Imperas site and on the OVP Fast Processor model see the OVPworld site.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32_r1r5/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.
Information on the 1004Kf OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library
http://www.ovpworld.org: Advanced Simulation Control of Platforms and Modules User Guide
http://www.ovpworld.org: Using OVP models with OSCI SystemC TLM2.0 platforms to gain 200-500 MIPS performance
Currently available Instruction Set Simulator (ISS) Families.